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1/12 AN1515 application note february 2002 1 introduction the lis1r02 is a complete rotational accelerometer system based on a capacitive sensor that uses mems technology, and a set of accompanying electronics that produces a digital output. the device is interfaced to external hardware using a standard 3-wire serial interface that allows internal registers to be written and rota- tional acceleration samples to be read. the mems structure consists of a rotor and stator assembly in which capacitive variations occur when the rel- ative position of the rotor with respect to the stator changes. these capacitive variations are on the order of 50 x 10-18 farads. the mems structure also includes actuation electrodes that allow the rotor position to be driven externally by the processing electronics. the electronic processing circuitry processes the capacitive variations that occur between the mems rotor and stator. a sigmadelta architecture is implemented that works to continually restore the rotor to nominal position. the control effort, or the signal that drives the rotor to nominal, represents the rotational acceleration that is present at the system location. this control effort is a binary bit stream that is decimated by the electronics to provide a noise-reduced output gain and offset adjustments are applied to the decimated bit stream to produce the acceleration samples. ac- celerometer samples then are clocked into a four-deep data fifo within the ic. the decimation and fifo stag- es are clocked in a free-running manner based on the selection of either an internal or external clock source. 1.1 choosing an external clock source designers who will use the lis1r02 to select the clock source which can be either from the clk_in pin, from the internal oscillator or generated by using an embedded pll. when the clk pin is selected as clock source, the designer has the ability to control the rate at which rotational acceleration samples are generated within the lis1r02. it takes exactly 224 clk_in cycles to generate one new rotational acceleration sample, therefore the formula for determining the optimal frequency of the clk_in signal is as follows: (eq. 2.1) where fclkin is the frequency of the clock signal that is applied to the clk_in pin and fout si the frequency at which samples are produced. if it is possible for the designer to implement a clk_in signal that satisfies equation 2.1 perfectly, then the de- vice will generate one new acceleration sample at the desired rate (1/ts). in practice, most designers will find it difficult to supply a clock whose frequency satisfies equation 2.1. generally, the designer will be restricted to using a signal for clk_in that only approximates equation 2.1. in this case, the acceleration samples will be generated at a rate that differs from the desired sample rate. the inclusion of the on-chip fifo data buffer allows for the proper handling of the accelerometer samples that are produced by the device. in the case where: (eq. 2.2) f out f clkin 224 ------------------- = f clkin 224 ts --------- - < by f. pasolini lis1r02 (l6671): a digital output angular accelerometer
AN1515 application note 2/12 a double sample will occur at a regular interval. the interval is a function of the difference between the lis1r02 sample generation rate and the desired sampling rate (1/ts). this interval, in units of servo sample periods, can be determined with the expression: (eq. 2.3) for example, if f clkin = 2.00 mhz and ts = 124 m s, then the fifo will contain two valid samples on approxi- mately every 9.333 samples. conversely, if (eq. 2.4) then a missing or empty sample will occur at a regular rate. in either case, the handling of the samples must be done carefully to fully minimize the noise in the system. for the purpose of obtaining multiple samples per servo period, the designer can choose a clk_in frequency that is approximately equal to an integer multiple of the product seen in equation 2.1. (eq. 2.5) in this case, the accelerometer samples will be generated at a rate of approximately n samples per desired sam- ple period, where n could be equal to 1, 2, 3, or 4. the designer must note, however, that the maximum fre- quency of clk_in, according to specification, is 6mhz. when the internal oscillator is selected, the samples will be generated in a free-running manner, based on the internal clock rate. with the default settings, samples are generated at a rate of approximately 20khz. to allow the production of data samples at a desired rate, a digital pll has been embedded. in this case, the formulas to be used to calculate the frequency of the signals stated in figure 1 are: (eq. 2.6) to allow the pll to operate correctly, f ref must be at least equal to 5 khz. (eq. 2.7) (eq. 2.8) for a better understanding of the idf, odf and mf terms, please refer to the pll registers description. t double 1 ts ------ - f clkin 224 ------------------- 1 ts ------ - C ? ?? -------------------------------------- = f clkin 224 ts --------- - > f clkin n 224 ts --------- - = f refdiv f ref idf 1 + () ------------------------ - = f refdiv f ref idf 1 + () ------------------------ - = f dco f refdiv mf 1 + () f ref mf 1 + () idf 1 + () ------------------------ - == f refdiv f dco odf 1 + () --------------------------- - f ref mf 1 + () idf 1 + () odf 1 + () ----------------------------------------------------- ==
3/12 AN1515 application note figure 1. clock generation scheme 1.2 serial interface the serial interface interacts with the outside world with 3 wires: spe , spc and spd . it is used to write the data into the registers (registers block) which can also be read. 1.2.1 read & write register figure 2. read & write protocol osc . . iod[3:0] . . idf[3:0] x2 pd dco . . mf[9:0] . . odf[1:0] cs0 0 1 cs0 0 1 cs1 0 1 dsc reference signal pin_clk fifo_low read (from internal logic) adpll f osc f oscdiv f ref f refdiv f dco f osc dscr 1 0 pllt 0 1 spe opdn main ck spc spe spd rw id2 id1 id0 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0
AN1515 application note 4/12 spe is the serial port enable. it goes high at the start of the transmission and goes back low at the end. spc is the serial port clock. it is stopped high when spe is low (no transmission). spd is the serial port data. it is driven by the falling edge of spc . it should be captured at the rising edge of spc . the read register or write register command consists of 16 clocks or bits. a bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the rising edge of spe and the last bit (bit 15) starts at the last falling edge of spc just before the falling edge of spe . bit 0: rw bit. when 0, the data d(7:0) is written into the rac. when 1, the data d(7:0) from the rac is read. in this case, the chip will drive spd at the start of bit 8. bit 1-3: chip id. the chip id for the rac is id(2:0)=110. the lis1r02 accepts the command only when the id is valid (equal to 110). bit 4-7: address ad(3:0). this is the address field for the registers. bit 8-15: data d(7:0). this is the data that will be written (read) into (from) the register which address is ad(3:0). 1.2.2 read fifo figure 3. read fifo protocol the read fifo command consists of 24 clocks or bits: bit 0: read bit. the value is 1. bit 1-3: chip id. id(2:0)=110. bit 4-7: fifo address. the fifo has four registers grouped into two banks. the first bank consists of the first and the second register. the first register is the one written first since the last read. the second bank consists of the third and fourth register. 000x: address for the first bank 001x: address for the second bank bit 8-23: fifo data. the rac puts out first the data of the first register of the bank starting with the msb. 1.2.3 notice the serial interface allows the ic to work with the spe line tied high. the clock line has to be normally high (i.e. clock off-state = 1 as depicted in figure 2.). if the clock remains high beyond the time out period, the serial interface is reset. this feature allows a ic test to run at very low frequency using narrow clock pulses. if a packet is not completed correctly, the normal high clock will generate a port reset, flushing the data. the timeout period is set to be 280*t osc . thus, supposing to have f osc = 70 mhz, the timeout period will be 4 m s. spc spe spd rw id2 id1 id0 ad3 ad2 ad1 ad0 d7-0 d6-0 ...... d0-0 d7-1 d6-1 ...... d0-1
5/12 AN1515 application note 1.3 registers: array organization the internal registers are organized as follows: table 1. registers array notes: (*) value stored inside the embedded flash and loaded at boo due to the limited number of address bit (4) allowed by the spi protocol and the high number of registers present internally to the device, the registers have been spit and grouped into three banks. to switch between reg. bank 1, reg. bank 2 and reg. bank 3 it is necessary to access the miscellaneous reg. located @ address 1111. the registers not loaded at boot can be written also before the boot procedure is completed. no reading is allowed until the boot is done. the boot procedure takes 1800 clock pulses to be completed. more information are reported in the paragraphs below. address reg. bank 1 reg. bank 2 reg. bank 3 0000 fifo_low fifo_low fifo_low 0001 not used not used not used 0010 fifo_high fifo_high fifo_high 0011 not used not used not used 0100 ctrl_reg1 ctrl_reg1 ctrl_reg1 0101 ctrl_reg2 ctrl_reg2 ctrl_reg2 0110 pll_presc_mult flash_reg_1 pll_compare_reg 0111 pll_mult flash_reg_2 pll_rst_value_reg 1000 iir_a0 (*) gain_low (*) not used 1001 iir_a1 (*) gain_high (*) not used 1010 iir_a2 (*) offset_low (*) not used 1011 iir_b1 (*) offset_high (*) not used 1100 iir_b2 (*) curr_bandgap (*) not used 1101 iir_sign_bit (*) band_csact_reg (*) not used 1110 dsc_reg cs_trim (*) not used 1111 misc_reg misc_reg misc_reg
AN1515 application note 6/12 1.4 registers description the only registers that can be modified by the user are described in the section that follows. 1.4.1 control_reg (0100) table 2. clock source selection table 3. control bit pdn ien cs1 cs0 opdn b2 b1 b0 pdn chip power down 0: chip on (default value) 1: chip in power down mode ien interrupt enable: 0: interrupt signal available to the external 1: pad in high z (default value); cs1-cs0 clock source selection. for more information look at paragraph clock scheme by default are set to 00 opdn oscillator power down: 0: oscillator toggling (default value); 1: oscillator turned off b2-b0 control bit definition cs1 cs0 clock source 0 0 clock from clk pin 0 1 internal oscillator 1 0 clock from pll locking on clk pin 1 1 clock from pll locking on fifo_low reg. reading b2-b0 mode selection 000 normal mode (default) 001 not allowed 010 011 100 101 11x
7/12 AN1515 application note 1.4.2 control_reg2 (0101) table 4. dsc reference signal selection table 5. clock source selection dscr dsc cen owl1 owl0 ifb df so dscr delayed synchronous conversion reference. by default is set to 0. dsc delayed synchronous conversion enable 0: delayed synchronous conversion disabled 1: delayed synchronous conversion enabled (default value) cen clip enable on the offset and gain adjustment unit 0: clip disabled 1: clip enabled (default value) owl1-owl0 output word length selection see table below. ifb iir filter bypass 0: iir filter on (default value) 1: iir filter bypassed df decimation factor selection (normal mode only; no dsc) 0: decimate by 16 1: decimate by 32 (default value) so sinc order selection 0: 2nd order 1: 3rd order (default value) dscr delayed synchronous conversion reference 0 pin_clk or fifo_read_low, depending on cs0 value 1 input clock divider output owl1 owl0 output word length 0 0 8 bit (default mode) 0 1 16 bit 1 0 32 bit 1 1 32 bit
AN1515 application note 8/12 1.4.3 pll_presc_mult (0110 -reg. bank1-) this register contains the value used by the pll prescaler to divide the input reference clock and the most sig- nificant bit of the pll multiplication factor. both the parameters are expressed in unsigned binary format. 1.4.4 pll_mult (0111 -reg. bank 1-) this register contains the value used by the pll prescaler to divide the input reference clock and the most sig- nificant bit of the pll multiplication factor. both the parameters are expressed in unsigned binary format. 1.4.5 iir_a0 (1000 -reg. bank 1-) contains the lsb of the coefficient a0 used in the iir filter. the sign bit is a0_8 and is stored in register iir_sign_bit (address 1101 -reg. bank 1-). the complete coefficient a0_8-a0_0 is expressed in twos com- plement format. 1.4.6 iir_a1 (1001 -reg. bank 1-) contains the lsb of the coefficient a1 used in the iir filter. the sign bit is a1_8 and is stored in register iir_sign_bit (address 1101 -reg. bank 1-). the complete coefficient a1_8-a1_0 is expressed in twos com- plement format 1.4.7 iir_a2 (1010 -reg. bank 1-) contains the lsb of the coefficient a2 used in the iir filter. the sign bit is a2_8 and is stored in register iir_sign_bit (address 1101 -reg. bank 1-). the complete coefficient a2_8-a2_0 is expressed in twos com- plement format. idf3 idf2 idf1 idf0 odf1 odf0 mf9 mf8 idf3-idf0 pll input division factor (default: 0000) odf1-odf0 pll output division factor (default: 00) mf9-mf8 pll multiplication factors msb (default: 00) mf7 mf6 mf5 mf4 mf3 mf2 mf1 mf0 mf7-mf0 pll multiplication factors lsb (default: 11011111) a0_7 a0_6 a0_5 a0_4 a0_3 a0_2 a0_1 a0_0 a0_7-a0_0 lsbs of the coefficient a1 used inside the iir filter (lsb) a1_7 a1_6 a1_5 a1_4 a1_3 a1_2 a1_1 a1_0 a1_7-a1_0 lsbs of the coefficient a1 used inside the iir filter (lsb) a2_7 a2_6 a2_5 a2_4 a2_3 a2_2 a2_1 a2_0 a2_7-a2_0 lsbs of the coefficient a2 used inside the iir filter (lsb
9/12 AN1515 application note 1.4.8 iir_b1 (1011 -reg. bank 1-) contains the lsb of the coefficient b1 used in the iir filter. the sign bit is b1_8 and is stored in register iir_sign_bit (address 1101 -reg. bank 1-). the complete coefficient b1_8-b1_0 is expressed in twos com- plement format. 1.4.9 ir_b2 (1100 -reg. bank 1-) contains the lsb of the coefficient b2 used in the iir filter. the sign bit is b2_8 and is stored in register iir_sign_bit (address 1101 -reg. bank 1-). the complete coefficient b2_8-b2_0 is expressed in twos com- plement format. 1.4.10iir_sign_bit (1101 -reg. bank 1-) contains the sign bit for the coefficients used inside the iir filter. all the coefficients are expressed in twos com- plement format. 1.4.11dsc_reg (1110 -reg. bank 1-) contains the threshold value used to trigger the decimation when in delay synchronous conversion mode. b1_7 b1_6 b1_5 b1_4 b1_3 b1_2 b1_1 b1_0 b1_7-b1_0 lsbs of the coefficient b2 used inside the iir filter (lsb) b2_7 b2_6 b2_5 b2_4 b2_3 b2_2 b2_1 b2_0 b2_7-b2_0 lsbs of the coefficient b2 used inside the iir filter (lsb) x b2_8 b1_8 x x a2_8 a1_8 a0_8 b2_8 sign bit for coefficient b2 b1_8 sign bit for coefficient b1 a2_8 sign bit for coefficient a2 a1_8 sign bit for coefficient a1 a0_8 sign bit for coefficient a0 dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 dt7-dt0 dsc threshold
AN1515 application note 10/12 1.4.12misc_reg (1111) this register is used to switch between registers bank1 and registers bank2 and to select the division factor of the divider acting on the internal oscillator. it also allows to force a sw reset on the device. table 6. registers bank selection 1.4.13gain_lsb (1000 -reg. bank 2-) 1.4.14gain_msb (1001 -reg. bank 2-) 1.4.15offset_lsb (1010 -reg. bank 2-) res pllt iod3 iod2 iod1 iod0 bs1 bs0 res force sw reset on the device (active high) pllt pll test using an external clock source (0: pll clock from internal oscillator (default value); 1: clock from spe pad when t8 is high) iod3-iod0 internal oscillator divider (set to 1000 by default) bs1-bs0 registers bank select at reset bs1-bs0=00 making reg. bank 1 accessible by default bs1-bs0 registers bank selection 00 bank 1 01 bank 2 10 bank 3 11 not used gl7 gl6 gl5 gl4 gl3 gl2 gl1 gl0 gl7-gl0 8 lsb of the digital gain block gh7 gh6 gh5 gh4 gh3 gh2 gh1 gh0 gh7-gh0 8 msb of the digital gain block ol7 ol6 ol5 ol4 ol3 ol2 ol1 ol0 ol7-ol0 8 lsb of the digital offset correction value
11/12 AN1515 application note 1.4.16offset_msb (1011 -reg. bank 2-) 1.5 device initialization before using the device, the user must disable the delayed synchronous conversion option (bit dsc of ctrl_reg2) and set the sinc order (bit so of ctrl_reg2) to 2. this is achieved by writing 0010 0010 inside the ctrl_reg2 register. 1.6 circuit board and layout considerations in order to avoid, in the analog section, any kind of disturbances coming from the digital section, the 5v supply and the ground are split between analog lines and digital lines. for this reason the vdd_digital 5v supply and the gnd_digital ground have been added. the two 5v supply lines must be powered up and down si- multaneously (a maximum 0.3v difference between them is allowed. the two 5v supply lines and the two ground lines could be derived from a single low-voltage supply and a single ground but must be connected to the chip using two separate decoupling capacitors. the lis1r02 ic by default expects a master clock coming into the clk_in pin. this master clock frequency must be lower than 6mhz. a ground plane must be located under the chip to help prevent any disturbance to the lis1r02 sensor. each of the two power supplies requires decoupling capacitors. it is recommended that each vdd pin (analog and digital) have a 0.22 m f as near as possible to the chip pin. a 22 m f electrolytic capacitor on the supply line is also advised. as close as possible to the ref_cap pin (pin 8), two decoupling capacitors must be placed. a 0.22 m f electrolytic and a 220pf ceramic or polyester are strongly recommended. due to the high sensitivity of this device maximum care must be taken during board layout to avoid any kind of coupling between clk_in, power supplies and grounds tracks. in order to avoid any performance loss, the ref_cap pin and the board trace that connects it must be far from any kind of noisy signal (i.e. clk_in). oh7 oh6 oh5 oh4 oh3 oh2 oh1 oh0 oh7-oh0 8 msb of the digital offset correction value
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics a 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 12/12 AN1515 application note

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